| Experience: 3-5 years |
| Location: Bangalore |
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RTL, functional timing simulations, black/white box verification, design and documentation, process awareness, hands on hardware debug. |
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Defense related experience or experience in DSP algorithm implementation is a plus. |
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Knowledge/experience on memory, parallel and serial interfaces will help. |
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Experience in scripting and automation highly desirable. |
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Skill sets: |
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HDL languages |
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VHDL/Verilog |
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Scripting |
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TCL/Perl |
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Simulator |
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ModelSim/NCSim/Aldec |
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Synth and P&R tools |
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Synplify/Xilinx ISE/Altera Quartus/Lattice ISL Lever/Actel Libero |
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Debug tools |
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Chipscope/Signal tap/Reveal/Logic analyzer/Scopes. |
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