| Experience: 3-5 years |
| Location: Bangalore |
 |
RTL, functional timing simulations, black/white box verification, design and documentation, process awareness, hands on hardware debug. |
 |
Defense related experience or experience in DSP algorithm implementation is a plus. |
 |
Knowledge/experience on memory, parallel and serial interfaces will help. |
 |
Experience in scripting and automation highly desirable. |
 |
Skill sets: |
|
 |
HDL languages |
: |
VHDL/Verilog |
 |
Scripting |
: |
TCL/Perl |
 |
Simulator |
: |
ModelSim/NCSim/Aldec |
 |
Synth and P&R tools |
: |
Synplify/Xilinx ISE/Altera Quartus/Lattice ISL Lever/Actel Libero |
 |
Debug tools |
: |
Chipscope/Signal tap/Reveal/Logic analyzer/Scopes. |
|
|
|