Power optimization on feature–rich devices

In general, power optimization seems opposed to product feature enhancement. Power optimization on feature–rich devices is built with high degree of focus on optimizing power consumption based on the use case. In the case of a mobile or a tablet the ecosystem is now quite well developed for power optimization; processor chips are made with lower micron fabrication, they operate at lower operating voltages and support many operating modes like (active, idle, sleep, deep sleep etc…..), dynamic voltage and frequency scaling reduce processor power consumption. There are also power optimization schemes like AVS (Automatic Voltage Scaling) and DPS (Dynamic Power Scaling) to provide power scaling as required.

The ecosystem of chips for battery management  and power optimization on feature–rich devices allows the designer to develop schemes to minimize power consumption while supporting power hungry features. This is now the standard approach to power optimization in feature rich devices, but what if you need to implement power optimization on a power hungry device?

Power Optimization – Implementation

In the instance I mentioned above, the ecosystem is well developed and optimized and it is a matter of porting the right schemes onto the existing devices. During the course of development, we came across an instance where the power consumption of an IP Camera for surveillance application had to be limited to a certain number. This involved power hungry ARM+DSP, FPGA and Video Encoder/Decoders. Given that the processor was not made for power optimized operation, we had to look at other areas to control and optimize power. The two main approaches adopted were 1) to choose the right chips with various modes (active, sleep, reset. etc) and 2) build intelligence into the electrical design to power on/off devices based on the use case of the product.

Power optimization, Power optimization on feature–rich devicesGiven that the product had to operate in extended temperature grade; choice of the chips was not easy. Finally we chose video encoder/decoder chips that either have auto power down mode or external pin / register for putting the unit in power down mode. Certain chips like some of the video decoders did not have any of these, we had to control the reset and power to these chips. The FPGA chosen was from a low power family, we had an understanding that FPGA was a strong source of power consumption due to switching. This FPGA was built on a low-power 45nm, 9-metal copper layer, dual-oxide process technology to reduce power consumption. Also during bit file generation, the tool offers options to optimize the design for low power consumption built on realizing the hardware with lower switching. The leakage currents on I/Os were reduced by putting the unused I/Os in tri-state modes. Power optimization schemes were developed within the FPGA based on the use case to put the various decoders into power down mode. The controls were driven from software on the processor. Electrical design was made such that the chip controls were accessible as GPIOs or I2C based registers, Software enabled/disabled the right chips on board. We observed that the DDR memory consumed a lot of power hence we had to find a mechanism to put the memory devices into dynamic auto management mode.

The Power optimization on feature–rich devices schemes brought down the power consumption by certain levels but this was not sufficient. Given that we did not have an active power management infrastructure, the schemes designed had to be unilateral, static and could not be adaptive like in a mobile or tablet. Then we started looking at the soft cores used on the FPGA anpower management, power optimization, Power optimization on feature–rich devicesd made them use-case sensitive. The cores were switched off / reset when not required. Then the bank voltages were selectively enabled / disabled for further reduction of power consumption. Then we started looking at the leakage currents on pull up and pull down resistors in the design. This was used to very marginally reduce power consumption.

Presently we are looking at selectively using peripherals within the processor and map them to use cases. Overall, we have achieved close to 90% power reduction or power optimization. The interesting part of this exercise was to come up with mechanisms of power optimization and saving in a power hungry design. We generally are given leeway on power consumption when the customer needs high-end product features. In this case most interestingly, the power constraint was because of system design. The power budget constraint of the IP camera we were designing was determined by the efficiency of the cooling mechanism, power budget of the system etc. We realized that power budget constraint derives its motivation from various system design aspects and not only the battery life. It was a refreshing alternate perspective into power optimization on feature–rich devices!

*Published in EE Times India