CHAMP-WB

6U OpenVPX Virtex-7 Processor Card targeted specifically at wide-band, low latency applications that require large FPGA processing, wide input/output requirements, with minimal latency.

Intel SBC, Intel ATOM SBC, CHAMP-WB-min

Overview

The CHAMP-WB from Curtiss-Wright is a signal processing engine that belongs to the family of user-programmable Xilinx Virtex-7 FPGA based computing products. As a standalone card, the CHAMP-WB is designed to support any application that needs large amounts of I/O bandwidth coupled with significant FPGA processing and minimal delay. Its modular design supports both standard Virtex®7 – compatible FMC (VITA 57) mezzanine cards as well as providing for higher throughput modules such as the TADF-4300.

The CHAMP-WB, signal processing engine, is designed to meet the needs of embedded high-performance digital signal and image processing applications. The CHAMP-WB is the highest performance ADC/DAC module for Wideband, Low-Latency Electronic Warfare applications, that require large FPGA processing, wide input/output requirements

The CHAMP-WB signal processing engine couple the dense processing resources of a single large Virtex7 FPGA with two high-bandwidth enhanced FMC mezzanine sites on a rugged 6U OpenVPX™ (VITA 65) form factor module. The board’s data plane connects directly to the FPGA with support for Gen2 Serial RapidIO® (SRIO) data plane fabric. Alternate fabrics can also be supported with different FPGA cores. A Gen3 PCI Express® (PCIe) switch connected to the board’s expansion plane enables a single host card, such as Curtiss-Wright’s VPX6-1957 or CHAMP-AV8 to control multiple CHAMP-WB cards without utilizing data-plane bandwidth. Memory support on the CHAMP-WB includes two (2) 64-bit 4 GB DDR3L memory banks that provide up to 8 GB of on-card data capture or pattern generation capability. The CHAMP-WB features two (2) high-bandwidth FMC sites that have been enhanced with an auxiliary connector to provide additional I/O capability. Twenty back-plane SERDES links, which can operate up to 10.3 Gbps, and 16 LVDS pairs provide additional I/O capability.

The TADF-4300 module supports sampling in the 2nd Nyquist zone, to analyze signals up to 8 GHz and provides sub-30 ns latency for the ADC and sub 10ns for the DAC. Spurious Free Dynamic Range varies over frequency, and is >58 dB up to 3 GHz and decreases to 45 dB from 3 GHz to 6 GHz signal input frequency. ENOB varies linearly from 7.2 at low frequency, 6.5 at 3 GHz and 6.2 at 6 GHz.

TECHNICAL SPECIFICATIONS

  • Single user-programmable Xilinx Virtex-7 FPGAs (X690T or X980T), with
  • 8 GB DDR3L SDRAM in two banks
  • Four 4-lane serial data plane links to the backplane (support up to 10.3 Gbps data rates)
  • 16 LVDS pairs to the backplane
  • Two Mezzanine sites with support for FMC (VITA 57) or enhanced FMC
  • Onboard PCIe Gen3 switch
  • FXTools BSP and FPGA design kit with highly-optimized IP Blocks, development environment, reference designs, scriptable simulation test benches and software libraries
  • VxWorks and Linux variants available
  • 6U VPX VITA 48 1" pitch form factor