Digital Down Converter IP Core

A wide-band Digital Down Converter FPGA IP Core on Xilinx and Altera platforms that provides DSP logic required to down convert a desired frequency band. The Digital Down Converter FPGA Core is ideal for digital receivers used in defense and aerospace applications.

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Overview

A Digital Down Converter converts a digitized, band limited high sample rate signal to a lower frequency signal and at reduced sample rate while retaining all the information. Digital Down Converters (DDC) are used in high performance equipment, providing superior quality with ideal mixing without non-linear distortions, phase noise or temperature stability problems, fully controllable filters and decimation, and possibility of programmable digital channel equalization. However, digital down conversion requires high-speed analog-to-digital converter (ADC) and real time data processing. One of the main advantage of using an FPGA to implement DDC IP Core is speed and the option to customize the filter chain to meet exact requirements.

The Digital Down Converter FPGA IP Core from Mistral is a wide-band DDC,  typically used in digital receivers for defense and aerospace applications. The DDC IP Core provides the digital signal processing logic on FPGA required to down convert a desired frequency band using FPGAs. Mistral’s Digital Down Converter FPGA IP Core is designed to be Programmable (Run-time), customizable (of the IP), Optimal Resource utilization and support for Xilinx and Altera FPGAs.

The programmable Digital Down Converter FPGA IP Core provides digital signal processing (DSP) logic required to down-convert a desired frequency band with decimation factors of 2 to 16 in steps of 1. The principal components of the Digital Down Converter IP Core are the tuner (Mixer and NCO/DDS) and the polyphase decimating filters. Features such as input/output data widths, number of filter taps, decimation factors and provision for fixed or dynamically loadable filter coefficients of the DDC IP Core are customizable as per user requirements.

TECHNICAL SPECIFICATIONS

  • Digital Down Converter FPGA Input data width: 16 bits
  • DDC Output data width: 24 bits
  • Decimation rate (programmable): 2 to 16
  • Filter coeff. Width: 18
  • Dynamically reloadable coeff. : Yes
  • Programmable DDS frequency: Yes
  • Programmable DDS phase offset: Yes
  • DDS data width: 24 bits
  • Support spectrum flip: Yes
  • SFDR (DDS): > 120 dB
  • Output gain stage: Yes