DDC IP Core
A wide-band Digital Down Converter IP Core on Xilinx and Altera FPGAs that provides DSP logic required to down convert a desired frequency band. The Digital Down Converter IP Core is ideal for digital receivers used in defense and aerospace applications.
Digital Down Converter (DDC) converts a digitized, band limited high sample rate signal to a lower frequency signal and at reduced sample rate while retaining all the information. The main advantage of using an FPGA to implement the Digital Down Converter is the speed and the option to customize the filter chain to meet exact requirements.
The Digital Down Converter FPGA (DDC IP Core) from Mistral is a wide-band Digital Down Converter IP Core typically used in digital receivers for defense and aerospace applications. The Digital Down Converter IP Core provides the digital signal processing logic on FPGA required to down convert a desired frequency band on FPGAs. The Digital Down Converter FPGA IP Core from Mistral is designed to be Programmable (Run-time), Customizable (of the IP), Optimal Resource utilization and support for Xilinx and Altera FPGAs.
The programmable Digital Down Converter IP core provides digital signal processing (DSP) logic required to down-convert a desired frequency band with decimation factors of 2 to 16 in steps of 1. The principal components of the DDC IP core are the tuner (Mixer and NCO/DDS) and the polyphase decimating filters. Features such as input/output data widths, number of filter taps, decimation factors and provision for fixed or dynamically loadable filter coefficients of the DDC IP Core are customizable as per user requirements.
- Digital Down Converter FPGA Input data width: 16 bits
- Digital Down Converter Output data width: 24 bits
- Decimation rate (programmable): 2 to 16
- Filter coeff. Width: 18
- Dynamically reloadable coeff. : Yes
- Programmable DDS frequency: Yes
- Programmable DDS phase offset: Yes
- DDS data width: 24 bits
- Support spectrum flip: Yes
- SFDR (DDS): > 120 dB
- Output gain stage: Yes